Display devices having an active matrix substrate on which a switching element is provided for each pixel have been widely used. An active matrix substrate including thin film transistors (hereinafter “TFTs”) as switching elements is referred to as a TFT substrate. Note that in the present specification, a portion of a TFT substrate that corresponds to a pixel of a display device may also be referred to as a pixel.
In recent years, it has been proposed to use an oxide semiconductor as the material of the active layer of a TFT, instead of an amorphous silicon or a polycrystalline silicon. Such a TFT is referred to as an “oxide semiconductor TFT”. An oxide semiconductor has a higher mobility than an amorphous silicon. Therefore, an oxide semiconductor TFT is capable of operating faster than an amorphous silicon TFT. Since an oxide semiconductor film is formed by a simpler process than a polycrystalline silicon film, it is applicable to a device that is required to have a large area.
Typically, a TFT substrate using an oxide semiconductor TFT includes, for each pixel, an oxide semiconductor TFT (hereinafter referred to simply as a “TFT”.) supported on a substrate, and a pixel electrode electrically connected to the drain electrode (drain metal) of the TFT. The TFT is normally covered by an interlayer insulating layer. The pixel electrode is provided on the interlayer insulating layer, and is connected to the drain electrode of the TFT in a contact hole formed in the interlayer insulating layer. The configuration of such a TFT substrate is disclosed in Patent Document No. 1, for example.
With the configuration disclosed in Patent Document No. 1, a drain electrode (typically, a metal electrode) having a pattern that is slightly larger than the bottom surface of a pixel contact hole is arranged in a pixel. This presents a factor for lowering the ratio of the light-transmitting region with respect to the pixel (hereinafter “pixel aperture ratio”). Although the source bus line and the drain electrode are typically formed by patterning the same metal film, as the definition of a display device increases and the area of each pixel decreases, the interval between the source bus line and the drain electrode decreases, thus making processing more difficult.
On the other hand, a configuration in which the pixel electrode is arranged so as to be in direct contact with the oxide semiconductor layer of the TFT is proposed in Patent Document No. 2 by the same applicant. FIGS. 13(a) and 13(b) are a plan view and a cross-sectional view, respectively, illustrating a TFT substrate 2000 disclosed in FIG. 3 and FIG. 4 of Patent Document No. 2. The TFT substrate 2000 includes a substrate 921, a TFT supported on the substrate 921, an interlayer insulating layer (flattening film) 926 covering the TFT, and a pixel electrode 928. The TFT includes a gate electrode 922, a gate insulating layer 923, an oxide semiconductor layer 924, and a source electrode 925s. The source electrode 925s is formed from a metal film having a layered structure, and is arranged so as to be in contact with the upper surface of the oxide semiconductor layer 924. The pixel electrode 928 is provided on the interlayer insulating layer 926 and in a contact hole 927 formed in the interlayer insulating layer 926, and is in direct contact with the oxide semiconductor layer 924 in the contact hole 927. That is, a part of the pixel electrode 928 functions as the drain electrode.
In the present specification, a portion of the oxide semiconductor layer 924 that is in contact with the pixel electrode 928 is referred to as a drain contact region 924ad, and a portion thereof that is in contact with the source electrode 925s as a source contact region. A channel region 924ac of the oxide semiconductor layer 924 refers to a portion that is located between the source contact region and the drain contact region 924ad and that overlaps the gate electrode 922 with the gate insulating layer 923 therebetween. A connecting portion that directly connects together the pixel electrode 928 and the oxide semiconductor layer 924 is referred to as a “pixel contact portion”, and the contact hole 927 formed in the interlayer insulating layer 926 for connecting together the pixel electrode 928 and the oxide semiconductor layer 924 as a “pixel contact hole”. The plan view of FIG. 13(a) shows the bottom surface of the pixel contact hole 927 (i.e., the base surface exposed by the pixel contact hole).